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vishay siliconix dg417l, dg418l, dg419l document number: 71763 s11-0598-rev. f, 25-apr-11 www.vishay.com 1 this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 precision monolithic low-volt age cmos analog switches description the dg417l, dg418l, dg419l are low voltage pin-for-pin compatible companion device s to the industry standard dg417, dg418, dg419 wi th improved performance. using bicmos wafer fabrication technology allows the dg417l, dg418l, dg419l to operate on single and dual supplies. single supply voltage ranges from 3 v to 12 v while dual supply operation is recommended with 3 v to 6 v. combining high speed (t on : 28 ns), flat r on over the analog signal range (6 ? ), minimal insertion lose (up to 100 mhz), and excellent crosstalk and off-isolation performance (- 70 db at 1 mhz), the dg417l, dg418l, dg419l are ideally suited for audio and video signal switching. the dg417l and dg418l respond to opposite control logic as shown in the truth table. the dg419l has an spdt configuration. features ? 2.7 v- thru 12 v single supply or 3- thru 6 dual supply ? on-resistance - r on : 14 ? ? fast switching - t on : 28 ns - t off : 13 ns ? ttl, cmos compatible ? low leakage: < 100 pa ? compliant to rohs directive 2002/95/ec applications ? precision automatic test equipment ? precision data acquisition ? communication systems ? battery powered systems ? computer peripherals ? sdsl, dslam ? audio and video signal routing benefits ? widest dynamic range ? low signal errors and distortion ? break-before-make switching action ? simple interfacing functional block diagram and pin configuration * pb containing terminations are not rohs compliant, exemptions may apply truth table logic dg417l dg418l 0onoff 1offon ordering information (dg417l, dg418l) temp. range package part number 8-pin narrow soic dg417ldy dg417ldy-e3 dg417ldy-t1 dg417ldy-t1-e3 dg418ldy dg418ldy-e3 dg418ldy-t1 dg418ldy-t1-e3 8-pin msop DG417LDQ-T1-E3 dg418ldq-t1-e3 1 dual-in-line, msop-8 and soic-8 nc/no com * v- gnd in v+ v l 2 3 4 8 7 6 5 t op v iew dg417l, dg418l * not connected truth table (dg419l) logic nc no 0onoff 1offon ordering information (dg419l) temp. range package part number - 40 c to 85 c 8-pin narrow soic dg419ldy dg419ldy-e3 dg419ldy-t1 dg419ldy-t1-e3 8-pin msop dg419ldq-t1-e3 1 dual-in-line, msop-8 and soic-8 com no nc v - gnd in v+ v l 2 3 4 8 7 6 5 top view dg419l
www.vishay.com 2 document number: 71763 s11-0598-rev. f, 25-apr-11 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. signals on nc, no, com, or in exceeding v+ or v- will be clamped by internal di odes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6.5 mw/c above 25 c. d. derate 12 mw/c above 75 c. absolute maximum ratings parameter limit unit v+ to v- - 0.3 to 13 v gnd to v- 7 v l (gnd - 0.3) to (v+) + 0.3 i n , com, nc, no a - 0.3 to (v+ + 0.3) or 30 ma, whichever occurs first continuous current (any terminal) 30 ma peak current, s or d (pulsed 1 ms, 10 % duty cycle) 100 storage temperature (ak, dq, dy suffix) - 65 to 150 c power dissipation (packages) b 8-pin msop c 320 mw 8-pin soic c 400 8-pin cerdip d 600 specifications (single supply 12 v) parameter symbol test conditions unless otherwise specified v+ = 12 v, v- = 0 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix limits - 55 c to 125 c d suffix limits - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 012012v on-resistance r on v+ = 10.8 v, v- = 0 v i no , i nc = 5 ma, v com = 2 v / 9 v room full 13 20 32 20 23.5 ? switch off leakage current i no(off) i nc(off) v com = 1 v / 11 v v no , v nc = 11 v / 1 v room full - 1 - 15 1 15 - 1 - 10 1 10 na i com(off) room full - 1 - 15 1 15 - 1 - 10 1 10 channel on leakage current i com(on) v no , v nc = v com = 11 v / 1 v room full - 1 - 15 1 15 - 1 - 10 1 10 digital control input current i inl or i inh full 0.01 - 1.5 1.5 - 1 1 a dynamic characteristics tu r n - o n t i m e t on r l = 300 ? , c l = 35 pf v no , v nc = 5 v, see figure 2 room full 28 43 50 43 46 ns turn-off time t off room full 13 31 35 31 32 break-before-make time delay t d dg419l only, v nc , v no = 5 v r l = 300 ? , c l = 35 pf room 13 charge injection e q inj v g = 0 v, r g = 0 ? , c l = 1 nf room 1 pc off-isolation e oirr r l = 50 ? , c l = 5 pf , f = 1 mhz room - 71 db channel-to-channel crosstalk e x ta l k room - 71 source off capacitance e c no(off) c nc(off) v in = 0 or v+, f = 1 mhz room 5 pf channel-on capacitance e c on room 15 power supplies positive supply current i+ v in = 0 or v l room full 0.02 1 7.5 1 5 a negative supply current i- room full - 0.002 - 1 - 7.5 - 1 - 5 logic supply current i l room full 0.002 1 7.5 1 5 ground current i gnd room full - 0.002 - 1 - 7.5 - 1 - 5
document number: 71763 s11-0598-rev. f, 25-apr-11 www.vishay.com 3 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 specifications (dual supply 5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, v- = - 5 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix limits - 55 c to 125 c d suffix limits - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full - 55- 55v on-resistance r on v+ = 5 v, v- = - 5 v i no , i nc = 5 ma, v com = 3.5 v room full 14 18.5 30 18.5 21 ? switch off leakage current a i no(off) i nc(off) v+ = 5.5 , v- = - 5.5 v v com = 4.5 v v no , v nc = 4.5 v room full - 1 - 15 1 15 - 1 - 10 1 10 na i com(off) room full - 1 - 15 1 15 - 1 - 10 1 10 channel on leakage current a i com(on) v+ = 5.5 v, v- = - 5.5 v v no , v nc = v com = 4.5 v room full - 1 - 15 1 15 - 1 - 10 1 10 digital control input current a i inl or i inh full 0.05 - 1.5 1.5 - 1 1 a dynamic characteristics tu r n - o n t i m e e t on r l = 300 ? , c l = 35 pf v no , v nc = 3.5 v, see figure 2 room full 30 41 50 41 44 ns turn-off time e t off room full 16 32 36 32 33 break-before-make time delay e t d dg419l only, v no , v nc = 3.5 v r l = 300 ? , c l = 35 pf room 10 transitiontime t trans r l = 300 ? , c l = 35 pf v s1 = 3.5 v, v s2 = 3.5 v room 33 47 47 charge injection e q inj v g = 0 v, r g = 0 ? , c l = 1 nf room 3 pc off-isolation e oirr r l = 50 ? , c l = 5 pf , f = 1 mhz room - 71 db channel-to-channel crosstalk e x ta l k room - 76 source off capacitance e c no(off) c nc(off) f = 1 mhz room 5.2 pf channel-on capacitance e c on room 15 power supplies positive supply current e i+ v in = 0 or v l room full 0.03 1 7.5 1 5 a negative supply current e i- room full - 0.002 - 1 - 7.5 - 1 - 5 logic supply current e i l room full 0.002 1 7.5 1 5 ground current e i gnd room full - 0.002 - 1 - 7.5 - 1 - 5
www.vishay.com 4 document number: 71763 s11-0598-rev. f, 25-apr-11 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 specifications (single supply 5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, v- = 0 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix limits - 55 c to 125 c d suffix limits - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 5 5 v on-resistance e r on v+ = 4.5 v, i no , i nc = 5 ma v com = 1 v, 3.5 v room full 26 36.5 50 36.5 40.5 ? dynamic characteristics tu r n - o n t i m e e t on r l = 300 ? , c l = 35 pf v no , v nc = 3.5 v, see figure 2 room full 37 49 60 49 54 ns turn-off time e t off room full 16 31 35 31 32 break-before-make time delay e t d dg419l only, v no , v nc = 3.5 v r l = 300 ? , c l = 35 pf room 19 charge injection e q inj v g = 0 v, r g = 0 ? , c l = 1 nf room 0.4 pc power supplies positive supply current e i+ v in = 0 or v l room full 0.02 1 7.5 1 5 a negative supply current e i- room full - 0.002 - 1 - 7.5 - 1 - 5 logic supply current e i l room full 0.002 1 7.5 1 5 ground current e i gnd room full - 0.002 - 1 - 7.5 - 1 - 5
document number: 71763 s11-0598-rev. f, 25-apr-11 www.vishay.com 5 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. leakage parameters are guaranteed by worst case te st condition and not subject to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, no t subject to production test. f. v in = input voltage to perform proper function. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications (single supply 3 v) parameter symbol test conditions unless otherwise specified v+ = 3 v, v- = 0 v v l = 3 v, v in = 2 v, 0.4 v f temp. b typ. c a suffix limits - 55 c to 125 c d suffix limits - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0 3 0 3 v on-resistance r on v+ = 2.7 v, v- = 0 v i no , i nc = 5 ma, v com = 0.5 v, 2.2 v room full 47 70 80 70 75 ? switch off leakage current a i no(off) i nc(off) v+ = 3.3 , v- = 0 v v com = 1, 2 v, v no , v nc = 2, 1 v room full - 1 - 15 1 15 - 1 - 10 1 10 na i com(off) room full - 1 - 15 1 15 - 1 - 10 1 10 channel on leakage current a i com(on) v+ = 3.3 v, v- = 0 v v no , v nc = v com = 1 v, 2 v room full - 1 - 15 1 15 - 1 - 10 1 10 digital control input current a i inl or i inh full 0.005 - 1.5 1.5 - 1 1 a dynamic characteristics tu r n - o n t i m e t on r l = 300 ? , c l = 35 pf v no , v nc = 1.5 v, see figure 2 room full 65 75 95 75 85 ns turn-off time t off room full 26 41 45 41 43 break-before-make time delay t d dg419l only, v no , v nc = 1.5 v r l = 300 ? , c l = 35 pf room 33 charge injection e q inj v g = 0 v, r g = 0 ? , c l = 10 nf room 1 pc off-isolation e oirr r l = 50 ? , c l = 5 pf , f = 1 mhz room - 71 db channel-to-channel crosstalk e x ta l k room - 77 source off capacitance e c no(off) c nc(off) f = 1 mhz room 5.6 pf channel on capacitance e c d(on) room 16
www.vishay.com 6 document number: 71763 s11-0598-rev. f, 25-apr-11 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) r on vs. v com and supply voltage r on vs. analog voltage and temperature supply current vs. input switching frequency 0 10 20 30 40 50 60 03 69 12 v+ = 2.7 v v com - analog v oltage (v) - on-resistance ( ) r on v+ = 4.5 v v+ = 10.8 v t = 25 c i s = 5 ma 0 5 10 15 20 25 30 - 5 - 3 - 1 1 3 5 - 40 c v = 5 v i s = 5 ma v co m - analog voltage (v) - on-resistance ( ) r on 25 c 85 c 125 c - 55 c input switching frequency (hz) 10 100 1 k 10 k 100 k 1 m 10 m 1 10 n 100 n 1 m 10 m 1 10 100 supply current (na) i+ - r on vs. analog voltage and temperature supply current vs. temperature leakage current vs. temperature 0 10 20 30 40 50 60 70 80 012345 a = 125 c b = 85 c c = 25 c d = - 4 0 c e = - 5 5 c i s = 5 ma - on-resistance ( ) r on v com - analog v oltage (v) v+ = 4.5 v v+ = 2.7 v a b c a b c d e d e 100 1000 10 000 - 5 5 - 35 - 15 5 25 45 65 85 105 125 temperature (c) supply current (na) i+ - v = 5 v v in = 0 v 1 10 100 1000 10 000 - 5 5 - 35 - 1 5 5 25 45 65 85 105 125 temperature (c) leakage current (pa) i co m( on) v+ = 12 v v - = 0 v i co m ( of f)
document number: 71763 s11-0598-rev. f, 25-apr-11 www.vishay.com 7 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) leakage vs. analog voltage switching time vs. temperature and dual supply voltage switching threshold vs. supply voltage - 40 - 20 0 20 40 02468 1 0 12 v com , v no , v nc - analog voltage (v) i co m ( of f) /i co m( on) leakage current (pa) v+ = 12 v v - = 0 v i no ( o f f ) /i nc( on) - switching time (ns) 0 10 20 30 40 50 60 70 80 - 55 - 35 - 15 5 25 45 65 85 105 125 t on v+ = 3 v t on , t off temperature (c) t on v+ = 5 v t off v+ = 3 v t off v+ = 5 v t off v+ = 6 v t on v+ = 6 v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 - switching threshold (v) v+ - supply v oltage (v) v t v l = v+ switching time vs. temperature and single supply voltage insertion loss, off -isolation crosstalk vs. frequency charge injection vs. analog voltage) - switching t ime (ns) 0 10 20 30 40 50 60 70 80 90 - 5 5 - 35 - 15 5 25 45 65 85 105 125 t on v+ = 3 v t on , t off temperature (c) t on v+ = 5 v t on v+ = 12 v t off v+ = 5 v t off v+ = 12 v t off v+ = 3 v talk 0.1 - 110 1 - 30 10 - 70 - 50 100 1000 frequency (hz) - 90 oirr loss 10 - 10 loss, oirr, x (db) v+ = 3 v v- = 0 v r l = 50 - 12 - 10 - 8 - 6 - 4 - 2 0 2 4 6 8 10 12 - 6 - 4 - 2 0 2 4 6 8 1 0 1 2 v com - analog v oltage (v) q - charge injection (pc) v = 5 v v+ = 3 v v+ = 5 v v+ = 12 v
www.vishay.com 8 document number: 71763 s11-0598-rev. f, 25-apr-11 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 schematic diagram (typical channel) test circuits figure 1. level shift/ drive v in v l s v+ gnd v- d v- v+ figure 2. switching time logic input switch output 50 % 0 v t r < 5 ns t f < 5 ns 90 % t off t on v ou t note: logic input waveform is inverted for switches that have the opposite logic sense control c l (includes fixture and stray capacitance) v+ in r l r l + r on v ou t = v in no or nc com v- v ou t gnd v l c l 35 pf v- r l 300 v l v+ v in switch input switch output v inh v inl 0.9 x v ou t figure 3. break-before-make (dg419l) c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d in com v+ gnd v+ c l 35 pf v o r l 300 v inh v inl v l v l v- v-
document number: 71763 s11-0598-rev. f, 25-apr-11 www.vishay.com 9 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 4. transition time (dg419l) c l (includes fixture and stray capacitance) v l r l r l + r on v o = v s v- v+ in c l 35 pf r l 300 v o v s2 v s1 v- gnd + 15 v + 5 v 50 % logic input switch output v s1 t r < 5 ns t f < 5 ns 10 % t tr a n s 90 % v 01 v s2 v 02 t tr a n s no or nc com nc or no v inh v inl figure 5. charge injection c l 1 nf r g v o v+ com v- in v l v g gnd off on off v o v o in in dependent on switch configuration input polarity determined by sense of switch. v- v+ v l v in = 0 - v+ q = v o x c l no or nc figure 6. crosstalk (dg419l) no or nc x ta l k isolation = 20 log v out v in c = rf bypass com v s 0 v or 2.4 v in 50 r g = 50 v l v + gnd v - c cc v + v- v l v in nc or no v out
www.vishay.com 10 document number: 71763 s11-0598-rev. f, 25-apr-11 vishay siliconix dg417l, dg418l, dg419l this datasheet is subject to change without notice. the product described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a com posite of all qualified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see www.vishay.com/ppg?71763 . figure 7. off isolation r l 50 com 0 v, 2.4 v r g = 50 gnd v- c off isolation = 20 log v com v no/nc in c no or nc c c = rf bypass v- v+ v l figure 8. source/drain capacitances no or nc in com v l v+ gnd v - c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent cc v- f = 1 mhz v+ v l
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 71244 12-jul-02 www.vishay.com 1 msop: 8?leads jedec part number: mo-187, (variation aa and ba) n = 8l millimeters dim min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.25 - 0.38 8 b 1 0.25 0.30 0.33 8 c 0.13 - 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.65 bsc e 1 1.95 bsc l 0.40 0.55 0.70 4 n 8 5 0 4 6 ecn: t-02080?rev. c, 15-jul-02 dwg: 5867
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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